Essay: Memristors

CHAPTER 1: INTRODUCTION
Computers transform to the smaller, faster and more reliable devices year by year. Accordingly designing more efficient logic gates, as the basic blocks of the VLSI chips, are essential for circuit designers. Since the integration reached to its limits through the conventional technologies mainly the CMOS based VLSI designs the quest for the novel promising technologies was commenced.
Memristor is a passive element that has been fabricated recently and taken increasing attentions. Formemoryapplications, itisnon-volatile and has an extremely small size of a few nanometers.Less area and non-volatility are the most important properties of this element. Also Memristors compatibility for fabrication over CMOS structures makes it as a breakthrough for the VLSI design enhancement.
Since the invention of integrated circuits CMOS is the predominant technology over the last 30 years, Low power consumption, high speed and high integration are the most important advantages of CMOS technology. The sustained growth in CMOS VLSI technology is making transistors to ever smaller dimensions. It’s obvious that scaling transistors cannot continue forever.
The CMOS based circuits encounter serious problems and limitations for design issues such as process limitations e.g. lithography or the area constraints. Therefore new solutions should be developed to further extend Moor’s Law and scaling roadmap.The emergence of nanoscale devices was so hopeful for overcoming the limitations of CMOS technology.
One emerging challenge to validate hybrid CMOS and memristor circuit and system is the need of a SPICE-like simulator. The current approach is to replace the memristor with complicated equivalent circuit, which is however very time-consuming and somewhat inaccurate. In order to deal withdesignscomposedoflargenumberofmemristorsandalso other traditional devices such as CMOS transistors, this newly introduced memristor needs to be included into a circuit simulator like SPICE.
Memristive devices need to be considered similarly as we dealt with CMOS devices using physics-basedmodel with geometrical device parameter dependence. One critical perspective to achieve this objective is to identify and includethenon-conventionalstatevariablerelevantforthenew dynamic behaviour of memristive devices. In order to overcome these limitations,memristive devices is emerged as a promising technology.TheMemristor can be scaled down to lower than 10 nm and offer higher speed, lower space and non-volatility features. In addition Memristor is a good fit for fabrication with CMOS for hybrid CMOS-Memristor based circuits. Therefore implementing large integration digital circuits through this new novel element can make nano-electronic circuits a good nominee for today increasing demand for portable and low power applications. Memristive circuits can be used in variousapplications such as logic gates, memory, neuromorphic systems and analog circuits. The non-volatility of the Memristor is its prominent feature. So using Memristor in future memory devices like Resistive Random Access Memories (RRAM) will be inevitable.
CHAPTER 2 : LITERATURE REVIEW
In circuit theory there are three basic two-terminal devices namely-resistor, capacitorand inductor. These elements are de’ned by the relation between two of the fourfundamental circuit variables- current i, voltage v, charge q and ‘ux ??, where thetime derivative of charge q is current i and according to Faradays laws voltage v is thetime derivative of ‘ux ??. The resistor is de’ned with the relation between the voltage v and current i as dv = Rdi. The capacitor is de’ned with the relation between thecharge q and voltage v as dq = Cdv. The inductor is de’ned with the relation betweenthe ‘ux ?? and current i as d?? = Ldi. The discovery of the existence of the fourthfundamental circuit element came to light in 1971 when Prof. Leon Chua proposedthe missing relation between charge q and the ‘ux ?? through symmetry in ‘gure1.1 [1].
Prof. Leon Chua named this element memristor, which is the short for memoryresistor. The memristor has a memristance M and the functional relation between’ux ?? and charge q is given by d?? = Mdq. The already known passive twoterminal devices are the basic building blocks of modern electronics and are thereforeubiquitous in circuits.But we know that though some elements store information theyeventually decay out. Even if the state of one element changes, the information about the new state would be lost once the power is turned o’ and wait sometime. Thisbasic point may seem irrelevant but fundamentally this is very crucial. The capacityto store information without the need of a power source would represent a paradigmchange.
There have been several attempts to functionally and electrically mimic the neuron activity and its networks [1]. However, major challenge that deters the progress in VLSI implementations of brain-like logic gates is the scalability of the networks and its practical limitations in solving large variable Boolean logic problems.
The possibility to mimic the brain-like circuits and logic networks is a topic of intense debate. One possibility is to apply the threshold logic gates in designing conventional computational blocks, while other option is to develop a completely trainable architecture that does not strictly bind itself to conventional computing topologies. In this brief, we restrict the notion of the brain mimicking to develop a generalized memristive threshold logic (MTL) cell in application to designing conventional computing blocks. Nonetheless, this topic is one of the forefront challenges in development of on-chip brain computing, and would require us to investigate not just new circuit design logic, but also new devices and systems.
Threshold logic is the primary logic of human brain that inspires from the neuronal ‘ring and training mechanisms. The progress in threshold logic circuits [2] are often limited to implementation of logic gates with a few number of input variables; this leads to limited progress being made in the development of practical computing circuit topologies.
Memristorlike switching devices [3] unlike many other electronic devices has an interesting appeal in on-chip brain computing, as it offers switching state through its bi-level resistance values. Furthermore, these resistors are mapped to the binary memory space and offer the advantage of low on-chip area and low leakage currents.
We explore this aspect of memristor, and extend over our previous work [4] in designing fast Fourier transform (FFT) computing useful for signal processing applications, and vedic additions and multiplications for ef’cient Arithmetic Logic Unit design.
The resulting circuits can be used in combination with conventional CMOS circuits to develop threshold logic processor designs.
2.1BASIC THEORY OF MEMRISTORS
2.1.1ORIGIN OF MEMRISTORS
Prof. Leon Chua noted that there are six di’erent mathematical relations connecting pairs of the four fundamental circuit variables current i, voltage v, charge q and ‘ux??.The relation between these variable is deduced from Faradays law of Induction. A resistor is de’ned by the relationship between voltage v and current i (dv = Rdi), the capacitor is de’ned by the relationship between charge q and voltage v (dq = Cdv) and the inductor is de’ned by the relationship between ‘ux ?? and current i d?? = Ldi. In addition, the current i is de’ned as the time derivative of the charge q and according to Faradays law, the voltage v is de’ned as the time derivative of the ‘ux ??. This relation is shown in the ‘gure 2.1
Leon Chua compared the above model to that of Aristotles theory of matter.According to this theory all matter consists of earth, water, air and ‘re. Each of these elements exhibits two of the four fundamental properties moistness, dryness,coldness and hotness. This is shown in ‘gure 2.2. So depending on the abovetheory he saw a striking resemblance and predicted the existence of the fourth kindof element and called it memristor.
2.1.2 Definition of memristor
Memristor, is a contraction of memory resistor because its main function is toremember its history. The memristor is a two-terminal device whose resistance depends on the magnitude and polarity of the voltage applied to it and the length ofthe time that voltage has been applied. When this voltage is turned o’, the memristorremembers its most recent resistance until the next time you turn it on. The simplemodel of this is as shown in ‘gure2.3
Figure 2.3: Simple Model of Memristor
Memristor is either said to be a charge controlled or a ‘ux controlled dependingupon the relation between the ‘ux ?? and the charge q as a function of the other. Fora charge controlled memristor the relation between ‘ux and charge is expressed as afunction of electric charge q,
?? = f(q)(2.1)
Di’erentiating (2.1)
For a ‘ux controlled memristor the relation between ‘ux and charge is expressedas a function of ‘ux linkage ??
q = f(??) (2.6)
Di’erentiating (2.6)
2.1.3 Analogy of Memristors
Consider a resistor to be a pipe through which water ‘ows in a stream line.The water represents the ‘owing electric charge. The resistors obstruction to the ‘ow of charge is comparable to the diameter of the pipe: narrower the pipe, the greaterthe resistance and vice versa. The resistors have a ‘xed pipe diameter, but where amemristor is a pipe that changes diameter with the amount and the direction of thewater ‘ow that ‘ows through it. If the water ‘ow through this pipe is in one direction,it expands, becoming less resistive. Send the water in the opposite direction, the pipeshrinks making it more resistive. Another important aspect of it is that the memristorremembers its diameter when water last went through it. Turn o’the ‘ow of waterand the diameter of the pipe freezes until the water is turned back on. This showsthe main characteristic of a memristor making it very special. The analogy is shown in figure 2.4below
Figure 2.4 Analogy of Memristor.
2.1.4 ??-q Characteristics of Memristor
One of the main characteristics of a ??-q of a memristor is it is monotonically increasing. The memristance M(q) is the slope of the ??-q curve. Prof. Leon Chua postulated a passivity criterion, according to which a memristor is passive if and only if the memristance M(q) is non-negative . If M(q) ‘ 0, then the instantaneous power dissipated by the memristor, p(i) = M(q).[i(t)]2 , is always positive and so the memristor is a passive device.The typical curves are as shown in ‘gure2.5
Figure 2.5: ??-q curve of Memristor.
2.1.5 i-v Characteristics of a Memristor
An important characteristic of a memristor is the pinched hysteresis loop currentvoltage characteristics. For a memristor excited by a periodic signal, when thevoltage v(t) is zero, the current i(t) is also zero and vice versa. Thus both voltage v(t) and current i(t) have identical zero-crossing.Another feature of memristor is that the pinched hysteresis loop shrinks with the increase in the excitation frequency.If any device has the abovecharacteristics, then the device is either a memristor or a memristive device.When the excitation frequency increses towards infinity,the memristor behaves like a normal resistor.The characteristics are as shown in ‘gure 2.6 below.
2.2 MODEL AND WORKING OF MEMRISTOR FROM HP LABS
Stanley Williams and his group at the HP Labs realized the memristor in a deviceform. Their basic model had two platinum electrodes on the either end of thedevice. The surface of the bottom platinum wire was oxidized to make an extremelythin layer of platinum dioxide, which is highly conducting. Then they assembled adense ‘lm, only one molecule thick, of specially designed switching molecules. Overthis layer they deposited 2-3 nm layer of Ti metal and the ‘nal layer was the topplatinum electrode. After years of experiments, they ‘nally realized that what theyhave was a memristor, as their i-v characteristic are similar to the one proposed byChua. They observed that under the molecular layer, instead of platinum dioxide,there was only pure platinum. Above the molecular layer instead of titanium, theyfound an unexpected and unusual layer of titanium dioxide. The titanium dioxidewas not just the regular titanium dioxide, it has split itself up into two chemicallydi’erent layers. Adjacent to the molecules, the oxide was stoichiometric titaniumdioxide, meaning the ratio of oxygen to titanium was perfect, exactly 2 to 1. Butcloser to the platinum electrode, the titanium oxide was missing a tiny amount ofits oxygen, and it was called oxygen-de’cient TiO2’x where x is about 0.05. The schematic of the above description is as shown in ‘gure 2.7
Figure 2.7: Schematic of HP MR, where D is the device channel length and w is the length of the doped region.
The operation that was observed which could explain the above mechanism isthat if a positive voltage is applied to the top electrode of the device, it will repel theoxygen vacancies in the TiO2’x layer down into pure TiO2, that turns the TiO2 layer to TiO2’x and makes it conductive, thus turning the device on. When a negative voltage is applied the vacancies are attracted upward and back out of the TiO2 andthus the thickness of TiO2 layer would increase and turn o’ the device.This schematicis shown in ‘gure 2.8 What makes this special-memristive- is that when the voltageis turned o’, positive or negative, the oxygen bubbles do not migrate. They stay wherethey are, which means that the boundary between the two titanium dioxide layers isfrozen. That is how the memristor remembers how much voltage was last applied.
The mathematical model [9] of the HP Memristor is given by
Figure 2.8: Behavior of HP memristor when positive and negative voltages are applied.
2.3 LTSpice model of memristor
Biolek provided the Spice model of the memristor. Though PSpice and LTSpiceare similar in the nature of their analysis, but even though there wasn’t any analysisdone in LTSpice. The listing for the LTSpice model is included in the appendix. The model generated in LTSpice is as shown in ‘gure 2.9
Figure 2.9: Symbol of the model in LTSpice.
The physical model of the memristor is shown in ‘gure 2.7. The total resistanceof the doped and undoped regions is given by
resistance for w=0 and w=D. The ratio of the two resistances usually given as 102103. The speed of the movement of the boundary between the doped and undopedregions depend on the resistance of the doped area, on the passing current, and onother factors according to the equation given
3.1
In nanoscale devices, small voltages can yeild enormous electric ‘elds, which can secondarily produce signi’cant nonlinearities in ionic transport. These nonlinearities manifestthemselves particularly at the thin ‘lm edges, where the speed of boundary betweenthe doped and undoped regions gradually decrease to zero. This phenomenon, callednonlinear dopant drift, can be modeled by the so-called window function f(x) on theright of (3.1).
The window function is given by
3.2
where p is a positive integer. The di’erences between the models with linear andnon-linear drift disappears when p increases.
CHAPTER 3: BASIC MEMRISTOR THRESHOLD LOGIC (MTL)CELL DESIGN
The MTL cell shown in Fig. 3.1 is the basic cell, which consists of two parts: 1) a memristor based input voltage averaging circuit and 2) an output threshold circuit.
Fig. 3.1MTL cell
In contrast to resistive threshold logic [4], the proposed cell has the input potential divider circuit modi’ed by removing the pull-down resistor to form an input voltage averaging circuit and the threshold circuit modi’ed with the combined use of operational ampli’er (op amp) and CMOS inverter. In particular, by removing the pull-down resistor from [4], an important improvement over lower power dissipation is achieved in cell as shown in Table I.
TABLE I COMPARING RESISTIVE THRESHOLD LOGIC CELL WITHPRESENT PROPOSED CIRCUIT BY IMPLEMENTING A TWO INPUT NOR LOGICGATE
In this brief, the threshold unit consisting of a combination of an op-amp [5] and a CMOS inverter that allows for fault tolerance in terms of logical output signal stability. The generalization of the cell to work as different logic gates is achieved with the ability of the cell to utilize a wider range of threshold value.
For an N input cell, the resistance circuit part consist of N memristors having equal memristance values, M1 = M2 =”’MN = M.The output voltage VA for N input voltages VI can be represented as
Table II shows truth table for two input NANDand NOR gates. V1 and V2 are the input voltage that can take values of VL(voltage low) or VH(voltage high). For practical purposes, the boundary conditions are avoided, and in general for any N inputs, if VREF is in between ((N ‘1)VH + VL)/N and VH, we obtain NAND logic, and if it is in between VL and (VL +(N ‘1)VH)/N, we obtain NOR logic. The combined effect of VREF at op-amp and VTH of the inverter provides a stable threshold logic unit, where VTH is the threshold voltage of the inverter.The op-amp ensures a wider range of threshold value limiting the role of inverter as a means to ensure stable binary states.The input and output simulation signal waveforms of the two input proposed cell with nor logic are shown in results.
Table 2:Truth Table for the MTL Cell in NAND and NOR logic
3.2: CIRCUIT DIAGRAM OF TWO INPUT PROPOSED MTLCELL WITH OP-AMP AS (i)OR GATE(ii)AND GATE AND (iii) XOR gate
Figure:3.2:circuit diagram of two input proposed mtlcell with op-amp as (i)or gate(ii)and gate and (iii) xor gate
Fig. 3.2 shows the circuit diagrams of OR, AND, andXOR functions implemented using the proposed NOR logic cell, where the VREF = VL +?? with ?? representing the incremental threshold value required for the functional implementation of threshold logic cell.We use the non-ideal resistive switching model of memristor reported in [4] for our study with an area of 10 nm ?? 10 nm and resistances in the range of [10-6ohm, 10-12 ohm], while CMOS circuits uses 0.25 ??m (both in the MTL and CMOS logics) Taiwan Semiconductor ManufacturingCompany technology to re’ect the practical applicability in standard silicon technologies. The memristor model has a nonideal behavior and consider the boundary effects.Here VREF = VL +?? where ?? representing the incremental threshold value required for the functional implementation of threshold logic cell.As the number of input increases, the voltage range in which a threshold can be ‘xed will get narrow. Hence, for each number of inputs, the threshold value VREF have to be ‘xed separately. To avoid this problem, a VREFvalue close to VL and VHfor NOR and NAND con’guration should be selected. VL +?? is a voltage value that is close to VLand less than ((N ‘ 1)VL + VH)/N. This will give the freedom of using the cell without changing VREF for increased number of inputs.The input and output simulation waveforms of two input proposed cell as AND logic gate and XOR logic gate are shown in results.
3.3MEMRISTIVE THRESHOLD FFT CIRCUIT
FFT/IFFT is widely used in digital signal processing for various ‘lter implementations. The basic equation of four-point DFT is
(3.1)
Using equation(3.1), we can represent the signal ‘ow graph [10] of four-point DFT, as shown in Fig. 3.3(a)
Fig. 3.3 (a) Signal ‘ow graph of a four-point DFT processor.
Implementation of the FFT processor [11] can be done as shown in Fig. 3.3(b)
Figure3.3(b) : Block diagram of a four-point DFT processor.
Here all the inputs to the circuit are 8-bit long. We know the exponential term of a four-point DFT, i.e., e’j2??nk/4 =??1 or??j, the multiplications with ??1 and??j are trivial, and no multipliers are needed to implement them. Each FFT unit have four inputs and one correspondingFFT output. Inputs are given to the FFT units as shown in Fig. 3.3(a).
The inputs, which are to be subtracted, are complemented and added. From Fig. 3.3(a), it can be seen that the real part and the imaginary part of the ‘rst output in four-point FFT requires only addition operation. Hence, the inputs to the ‘rst two FFT units in Fig. 3.3(b) are not complimented. These FFT units are implemented using 3 carry-lookahead adders (CLA) as shown in Fig. 3.3(c).
Figure 3.3(c) Block diagram of FFT units used in the DFT processor.
Other than the ‘rst two FFT units, rest of the six FFT units have two additions and two subtractions. Inputs to be added are given to the ‘rst CLA, whereas the inputs that are to be subtracted are complimented and then added using the second CLA. To obtain the twos compliment, 1 is to be added to the least signi’cant bits (LSBs) of inverted inputs. For this, we utilize the C0 pin of the CLAs and a logic high is applied to the C0 pin of both the 8-bit CLA. This operation equates to adding one twice. Now, the outputs of these CLAs are added using the third CLA whose output result in the required transform. The CLAs are implemented using the proposed MTL circuits.
CHAPTER 4.MEMRISTOR BASED THRESHOLD VEDIC MULTIPLIER
Vedic multiplier is a multiplier architecture that uses Vedic mathematic [12] method for its multiplication algorithm. Among the sixteen methods presented in the Vedic mathematics, due to the parallelism in the mode of operation, we are using Urdhva Thirayakbhyam (vertical and crosswise method) [13] method for our multiplier architecture. In this technique, all the partial products can be found in parallel and the entire multiplication can be completed using additional two or three levels of adders.
Based on this algorithm, the architectural block diagram and the working principle for a 2-bit multiplier is shown in Fig. 4.1 below. Fig.4.1(a) shows the equivalent circuit of a 2-bit Vedic multiplier algorithm implemented using MTL and Fig. 4.1(b) shows the waveform of the corresponding circuit, where A0 A1 and B0 B1 are the 2-bit inputs and S0, S1, S2, andS3 are the four bits of the result. In this algorithm, the 2-bit multiplier is the basic multiplier unit that can be used for making the higher bit multipliers.
Figure : 4.1(a) (i) Architecture block diagram for a 2-bit Vedic multiplier. (a-ii) Working principle for each stage of the architecture. (b) Block diagram for an N bit multiplier
To implement an N-bit memristive threshold Vedic multiplier as shown in Fig. 4.1(b), we need four N/2-bit multipliers, two N-bit CLAs, one N/2-bit CLA, and a half adder, where N must be in thepower of 2. As shown in Fig. 4.1(b), using four 2-bit multipliers, we can implement 4-bit multiplier. Similarly, using four 4-bit multiplier, we can implement 8-bit multiplier and will continue the same procedure for any higher bits.
Suppose, the task is to implement a 8-bit multiplication then it would need four 4-bit multiplier, two 8-bit CLAs, one 4-bit CLA,and one half adder. First, the eight bits of both multiplicand and multiplier is divided into two 4-bit numbers. Let A and B be two eight bit numbers, where we divide A as (AH, AL) andB as (BH, BL). Similar to the steps that we followed in implementing 2-bit multiplier as explained in Fig. 4.1(a), we multiply this four 4-bit numbers (AH, AL, BH, andBL). The partial products are AL??BL, AH??BL, AL??BH, andAH??BH. Since these are independent operations, they are processed in parallel. While doing the multiplication, each of this 4-bit numbers (AH, AL, BH, andBL) will again divide into two 2-bit numbers, that is, AL as ALH and ALL, and proceed the 4-bit multiplication as explained in case of 8-bit (AL ?? BL ‘ ALL ?? BLL, ALL ?? BLH, ALH ?? BLL, ALH?? BLH). The basic multiplication unit is a 2-bit multiplier as shown in Fig. 4.2(a).
Figure: 4.2(a). Circuit diagram of 2 bit memristor based threshold vedic multiplier
Figure 4.3(a) shows input and output waveform of the 2 bit memristive threshold vedic multiplier, where A0 A1 andB0 B1 are the 2-bit inputs and S0, S1, S2, andS3 are the four bits of the output.
Table III shows the comparison of 2- and 8-bit Vedic multiplier using MTL and CMOS logic for area, power dissipation, and leakage power. From the table, it is clear that the proposed MTL architecture has a clear advantage over the existing CMOS technology. As an initial step to achieve small area on-chip brain computing, this realization is a promising result for the future developments in the ‘eld of cognitive computing circuits. For the 2-bit multiplier, all thecells are of two inputs and we implement the circuit with cells without op-amp as shown in Fig. 4.2(a). The op-amp is not required in this case, as large variation in threshold is not required to implement the threshold logic. For multiplier with higher number of bits, cells with op-amp are used to ensure tolerance to larger range of threshold values. This will increase the power dissipation as indicated in Table III. Like the FFT circuit, we expect to overcome this drawback by designing low-power op-amps in the circuit.
Table III
CHAPTER 5: SIMULATION RESULTS
Figure 5.1: Input and output simulation waveforms of two input proposed MTL cell in NOR logic
Figure 5.2: Input and output simulation waveforms of the two input proposed cell using XOR logic
Figure 5.3: Input and output simulation waveforms of two input proposed cell withopamp in AND logic
Figure 5.4: output and input simulation waveforms 2 bit vedic multiplier where A0 A1 and B0 B1 are the 2-bit inputs and S0,S1,S2,and S3 are the four bits of the output.
CHAPTER6 : CONCLUSION & FUTURE SCOPE
We have studied the basic theory,characteristics,model and working of memristors. The LT spice model of Memristor was also explored. The basic computing circuits like AND,NOR, and XOR with threshold logic MTL cell are designed, simulated and the truth table has been verified using LT spice simulation. Also memristive threshold FFT circuit is designed.The sum,carry and Cout of the 8th bit of the four inputs to an FFT unit is verified.Memristive threshold vedic multiplier is designed, simulated and the input and output wave forms of the circuit are verified using LT spice simulation. The simulated waveforms are shown in results.
Going forward,the future proposal is to show the effect on the higher point FFTs, we will implement a eight-point FFT using Vedic multipliers and CLAs with MTL and will do the performance comparison with CMOS technology. The advantage of the MTL is its lower on-chip area.
In comparison with CMOS logic the proposed MTL cell implementation have lower area requirements and higher power dissipation, and in comparison with other memristive-CMOS threshold logic gates the proposed cell indicate lower area requirements and lower power dissipation.The op-amp part of the circuit contributes the power dissipation and leakage power of the proposed logic. The developing low power high-speed op-amps aids the improvement of the same in future.
.
CHAPTER 7: BIBLIOGRAPHY
[1] A. P. James, L. R. V. J. Francis, and D. S. Kumar, ‘Resistive threshold logic,’ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 1, pp. 190’195, Jan. 2014.
[2] A. Rothenbuhler, T. Tran, E. H. B. Smith, V. Saxena, and K. A. Campbell, ‘Recon’gurable threshold logic gates using memristive devices,’ J. Low Power Electron. Appl., vol. 3, no. 2, pp. 174’193, 2013.
[3] J. Rajendran, H. Manem, R. Karri, and G. S. Rose, ‘An energy-ef’cient memristive threshold logic circuit,’ IEEE Trans. Comput., vol. 61, no. 4, pp. 474’487, Apr. 2012.
[4] Q. Xia et al. ‘Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines,’ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 8, pp. 1407’1417, Aug. 2011.
[5] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York, NY, USA: Oxford Univ. Press, 2011.
[6] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, ‘Nanoscale memristor device as synapse in neuromorphic systems,’ Nano Lett., no. 10, no. 4, pp. 1297’1301, 2010
[7] W. Li and L. Wanhammar, ‘Ef’cient radix-4 and radix-8 butter’y elements,’ in Proc. NorChip Conf., 1999, pp. 262’267.
[8] Q. Xia et al., ‘Memristor’CMOS hybrid integrated circuits for recon’gurable logic,’ Nano Lett., vol. 9, no. 10, pp. 3640’3645, 2009.
[9] R. Williams, ‘How we found the missing memristor,’ IEEE Spectrum, vol. 45, no. 12, pp. 28’35, Dec. 2008.
[10] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York, NY, USA: Wiley, 2007.
[11] V. Beiu, J. M. Quintana, and M. J. Avedillo, ‘VLSI implementations of threshold logic’A comprehensive survey,’ IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1217’1243, Sep. 2003.
[12] R. Pushpangadan, V. Sukumaran, R. Innocent, D. Sasikumar, and V. Sundar, ‘High speed vedic multiplier for digital signal processors,’ IETE J. Res., vol. 55, no. 6, pp. 282’286, 2009.
[13] B. K. Tirthaji, Vedic Mathematics. Jawahar Nagar, India: MotilalBanarsidass, 1965.
[14] Memristive Threshold Logic circuits as a Vedic Multiplier ZhaksylykKazykenov&SerikbolsynDuisembay Department of Electrical and Electronic Engineering
APPENDIX
Netlist for two bit memristive threshold vedic multiplier
VOS nvth 0 DC 0.1
VDD nvdd 0 DC 1
VSS nvss 0 DC -1
v1 in1 0 0
v2 in2 0 1
vgndgnd 0 0
vin1 na0 0 pulse(0 1 0 1n 1n 200n 400n)
vin2 na1 0 pulse(0 1 0 1n 1n 400n 800n)
vin3 nb0 0 pulse(0 1 0 1n 1n 800n 1600n)
vin4 nb1 0 pulse(0 1 0 1n 1n 1600n 3200n)
*v1 na0 0 1
*v2 na1 0 1
*v3 nb0 0 1
*v4 nb1 0 1
xmul s3 s2 s1 s0 na1 na0 nb1 nb0 nvddnvssnvthgnd 2bitmul
.tran 3200n
.subckt 2bitmul s3 s2 s1 s0 na1 na0 nb1 nb0 nvddnvssnvthgnd
xand1 s0 na0 nb0 nvddnvssnvthgnd and2
xand2 s2i na0 nb1 nvddnvssnvthgnd and2
xand3 s3i na1 nb0 nvddnvssnvthgnd and2
xand4 s4i na1 nb1 nvddnvssnvthgnd and2
x_xor5 s1 s2i s3i nvddnvssnvthgndxor
xand6 c6i s2i s3i nvddnvssnvthgnd and2
x_xor6 s2 s4i c6i nvddnvssnvthgndxor
xand7 s3 s4i c6i nvddnvssnvthgnd and2
.subcktxor out in1 in2 nvddnvssnvthgnd
x_or1 op1 in1 in1nvddnvssnvthgnd nor
x_or2 op2 in2 in2nvddnvssnvthgnd nor
x_or3 op3 in1 in2 nvddnvssnvthgnd nor
x_or4 op4 op1 op2 nvddnvssnvthgnd nor
x_or5 out op3 op4 nvddnvssnvthgnd nor
.subckt nor out2 in1 in2 nvddnvssnvthgnd
*vrefnref 0 .1
xr1 in1 nvo memristor
xr2 in2 nvo memristor
*xronvo 0 memristor
XOPAMP nvo out1 nvddnvssnvthgndopamp
M1 nvdd out1 out2 nvdd PMOS L=0.24U W=1U
M2 out2 out1 gndgnd NMOS L=0.24U W=.36U
*M3 nvdd out2 out nvdd PMOS L=0.24U W=1U
*M4 out out2 0 0 NMOS L=0.24U W=.36U
.subcktopampnvo op1 3 4 1 gnd
*VOS 1 0 DC 0.1
* Power Supplies
*VDD 3 0 DC 1
*VSS 4 0 DC -1
* Netlist for CMOS COMPARATOR in Pwell
M1 5 1 7 4 NMOS W=.24U L=.24U
M2 6 nvo 7 4 NMOS W=.24U L=.24U
M3 5 5 3 3 PMOS W=.31992U L=.24U
M4 6 5 3 3 PMOS W=.31992U L=.24U
M5 7 9 4 4 NMOS W=.24U L=.24U
M6 op1 6 3 3 PMOS W=2.55984U L=.24U
M7 op1 9 4 4 NMOS W=.96U L=.24U
M8 9 9 4 4 NMOS W=.96U L=.24U
* External Components
CL op1 gnd .2pF
RB 9 gnd 175K
* SPICE Parameters
.ends
.MODEL NMOS NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3728287
+K1 = 0.4864243 K2 = -1.409657E-4 K3 = 1E-3
+K3B = 2.825499 W0 = 1E-7 NLX = 1.888392E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.4506053 DVT1 = 0.550849 DVT2 = -0.5
+U0 = 288.0462132 UA = -1.405775E-9 UB = 2.623003E-18
+UC = 3.629325E-11 VSAT = 1.338206E5 A0 = 1.7824214
+AGS = 0.3184507 B0 = -3.027093E-8 B1 = -1E-7
+KETA = -7.187156E-3 A1 = 0 A2 = 0.5020225
+RDSW = 200 PRWG = 0.3401424 PRWB = 0.0544682
+WR = 1 WINT = 0 LINT = 3.714594E-12
+XL = 0 XW = -4E-8 DWG = -1.815918E-8
+DWB = 1.091895E-9 VOFF = -0.0921074 NFACTOR = 1.5957345
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 5.73523E-3 ETAB = 1.682537E-4
+DSUB = 0.038118 PCLM = 1.7102415 PDIBLC1 = 0.9099192
+PDIBLC2 = 3.201179E-3 PDIBLCB = 0.0309473 DROUT = 1
+PSCBE1 = 7.911377E10 PSCBE2 = 5.009298E-10 PVAG = 9.207919E-3
+DELTA = 0.01 RSH = 4 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.12E-10 CGSO = 4.12E-10 CGBO = 7E-10
+CJ = 1.79611E-3 PB = 0.99 MJ = 0.4682401
+CJSW = 4.500633E-10 PBSW = 0.9370045 MJSW = 0.3038281
+CJSWG = 3.29E-10 PBSWG = 0.9370045 MJSWG = 0.3038281
+CF = 0 PVTH0 = -7.974754E-3 PRDSW = -10
+PK2 = 5.306978E-3 WKETA = 8.666091E-3 LKETA = -9.033715E-3 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.5414189
+K1 = 0.6333125 K2 = 1.11193E-3 K3 = 0.0949758
+K3B = 10.0438776 W0 = 1E-6 NLX = 3.540373E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.6693896 DVT1 = 0.735565 DVT2 = -0.2439268
+U0 = 100 UA = 9.248319E-10 UB = 1E-21
+UC = -1E-10 VSAT = 1.577465E5 A0 = 0.9984451
+AGS = 0.1179402 B0 = 1.80539E-7 B1 = 8.788144E-7
+KETA = 0.0116764 A1 = 0.0252278 A2 = 0.3
+RDSW = 1.09093E3 PRWG = 0.150348 PRWB = -0.1482303
+WR = 1 WINT = 0 LINT = 2.8873E-8
+XL = 0 XW = -4E-8 DWG = -3.637876E-8
+DWB = -7.44149E-10 VOFF = -0.1180736 NFACTOR = 1.0742561
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.9070262 ETAB = -0.1833152
+DSUB = 1.5 PCLM = 1.3317254 PDIBLC1 = 8.162344E-3
+PDIBLC2 = 5.999554E-7 PDIBLCB = -4.026019E-4 DROUT = 0.1118588
+PSCBE1 = 8E10 PSCBE2 = 2.513346E-6 PVAG = 5.04939E-3
+DELTA = 0.01 RSH = 3 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.52E-10 CGSO = 4.52E-10 CGBO = 7E-10
+CJ = 1.86424E-3 PB = 0.985552 MJ = 0.4701753
+CJSW = 3.840487E-10 PBSW = 0.8 MJSW = 0.3085832
+CJSWG = 2.5E-10 PBSWG = 0.8 MJSWG = 0.3085832
+CF = 0 PVTH0 = 4.281542E-3 PRDSW = -0.4907077
+PK2 = 2.539815E-3 WKETA = 0.0275407 LKETA = -7.009864E-3 )
.SUBCKT memristor Plus Minus PARAMS:
+ Ron=10K Roff=100K Rinit=80K D=10N uv=10F p=1
***********************************************
* DIFFERENTIAL EQUATION MODELING *
***********************************************
Gx 0 x value={ I(Emem)*uv*Ron/D^2*f(V(x),p)}
Cx x 0 1 IC={(Roff-Rinit)/(Roff-Ron)}
Raux x 0 1T
* RESISTIVE PORT OF THE MEMRISTOR *
*******************************
Emem plus aux value={-I(Emem)*V(x)*(Roff-Ron)}
Roff aux minus {Roff}
***********************************************
*Flux computation*
***********************************************
Eflux flux 0 value={SDT(V(plus,minus))}
***********************************************
*Charge computation*
***********************************************
Echarge charge 0 value={SDT(I(Emem))}
***********************************************
* WINDOW FUNCTIONS
* FOR NONLINEAR DRIFT MODELING *
***********************************************
*window function, according to Joglekar
.func f(x,p)={1-(2*x-1)^(2*p)}
*proposed window function
;.func f(x,i,p)={1-(x-stp(-i))^(2*p)}
.ENDS memristor
.ends nor
.ends xor
.subckt and2 out in1 in2 nvddnvssnvthgnd
x_or1 op1 in1 in1nvddnvssnvthgnd nor
x_or2 op2 in2 in2nvddnvssnvthgnd nor
x_or3 out op1 op2 nvddnvssnvthgnd nor
.subckt nor out2 in1 in2 nvddnvssnvthgnd
*vrefnref 0 .1
xr1 in1 nvo memristor
xr2 in2 nvo memristor
*xronvo 0 memristor
XOPAMP nvo out1 nvddnvssnvthgndopamp
M1 nvdd out1 out2 nvdd PMOS L=0.24U W=1U
M2 out2 out1 gndgnd NMOS L=0.24U W=.36U
*M3 nvdd out2 out nvdd PMOS L=0.24U W=1U
*M4 out out2 0 0 NMOS L=0.24U W=.36U
.subcktopampnvo op1 3 4 1 gnd
*VOS 1 0 DC 0.1
* Power Supplies
*VDD 3 0 DC 1
*VSS 4 0 DC -1
* Netlist for CMOS COMPARATOR in Pwell
M1 5 1 7 4 NMOS W=.24U L=.24U
M2 6 nvo 7 4 NMOS W=.24U L=.24U
M3 5 5 3 3 PMOS W=.31992U L=.24U
M4 6 5 3 3 PMOS W=.31992U L=.24U
M5 7 9 4 4 NMOS W=.24U L=.24U
M6 op1 6 3 3 PMOS W=2.55984U L=.24U
M7 op1 9 4 4 NMOS W=.96U L=.24U
M8 9 9 4 4 NMOS W=.96U L=.24U
* External Components
CL op1 gnd .2pF
RB 9 gnd 175K
* SPICE Parameters
.ends
.MODEL NMOS NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3728287
+K1 = 0.4864243 K2 = -1.409657E-4 K3 = 1E-3
+K3B = 2.825499 W0 = 1E-7 NLX = 1.888392E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.4506053 DVT1 = 0.550849 DVT2 = -0.5
+U0 = 288.0462132 UA = -1.405775E-9 UB = 2.623003E-18
+UC = 3.629325E-11 VSAT = 1.338206E5 A0 = 1.7824214
+AGS = 0.3184507 B0 = -3.027093E-8 B1 = -1E-7
+KETA = -7.187156E-3 A1 = 0 A2 = 0.5020225
+RDSW = 200 PRWG = 0.3401424 PRWB = 0.0544682
+WR = 1 WINT = 0 LINT = 3.714594E-12
+XL = 0 XW = -4E-8 DWG = -1.815918E-8
+DWB = 1.091895E-9 VOFF = -0.0921074 NFACTOR = 1.5957345
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 5.73523E-3 ETAB = 1.682537E-4
+DSUB = 0.038118 PCLM = 1.7102415 PDIBLC1 = 0.9099192
+PDIBLC2 = 3.201179E-3 PDIBLCB = 0.0309473 DROUT = 1
+PSCBE1 = 7.911377E10 PSCBE2 = 5.009298E-10 PVAG = 9.207919E-3
+DELTA = 0.01 RSH = 4 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.12E-10 CGSO = 4.12E-10 CGBO = 7E-10
+CJ = 1.79611E-3 PB = 0.99 MJ = 0.4682401
+CJSW = 4.500633E-10 PBSW = 0.9370045 MJSW = 0.3038281
+CJSWG = 3.29E-10 PBSWG = 0.9370045 MJSWG = 0.3038281
+CF = 0 PVTH0 = -7.974754E-3 PRDSW = -10
+PK2 = 5.306978E-3 WKETA = 8.666091E-3 LKETA = -9.033715E-3 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.5414189
+K1 = 0.6333125 K2 = 1.11193E-3 K3 = 0.0949758
+K3B = 10.0438776 W0 = 1E-6 NLX = 3.540373E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.6693896 DVT1 = 0.735565 DVT2 = -0.2439268
+U0 = 100 UA = 9.248319E-10 UB = 1E-21
+UC = -1E-10 VSAT = 1.577465E5 A0 = 0.9984451
+AGS = 0.1179402 B0 = 1.80539E-7 B1 = 8.788144E-7
+KETA = 0.0116764 A1 = 0.0252278 A2 = 0.3
+RDSW = 1.09093E3 PRWG = 0.150348 PRWB = -0.1482303
+WR = 1 WINT = 0 LINT = 2.8873E-8
+XL = 0 XW = -4E-8 DWG = -3.637876E-8
+DWB = -7.44149E-10 VOFF = -0.1180736 NFACTOR = 1.0742561
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.9070262 ETAB = -0.1833152
+DSUB = 1.5 PCLM = 1.3317254 PDIBLC1 = 8.162344E-3
+PDIBLC2 = 5.999554E-7 PDIBLCB = -4.026019E-4 DROUT = 0.1118588
+PSCBE1 = 8E10 PSCBE2 = 2.513346E-6 PVAG = 5.04939E-3
+DELTA = 0.01 RSH = 3 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.52E-10 CGSO = 4.52E-10 CGBO = 7E-10
+CJ = 1.86424E-3 PB = 0.985552 MJ = 0.4701753
+CJSW = 3.840487E-10 PBSW = 0.8 MJSW = 0.3085832
+CJSWG = 2.5E-10 PBSWG = 0.8 MJSWG = 0.3085832
+CF = 0 PVTH0 = 4.281542E-3 PRDSW = -0.4907077
+PK2 = 2.539815E-3 WKETA = 0.0275407 LKETA = -7.009864E-3 )
.SUBCKT memristor Plus Minus PARAMS:
+ Ron=10K Roff=100K Rinit=80K D=10N uv=10F p=1
***********************************************
* DIFFERENTIAL EQUATION MODELING *
***********************************************
Gx 0 x value={ I(Emem)*uv*Ron/D^2*f(V(x),p)}
Cx x 0 1 IC={(Roff-Rinit)/(Roff-Ron)}
Raux x 0 1T
* RESISTIVE PORT OF THE MEMRISTOR *
*******************************
Emem plus aux value={-I(Emem)*V(x)*(Roff-Ron)}
Roff aux minus {Roff}
***********************************************
*Flux computation*
***********************************************
Eflux flux 0 value={SDT(V(plus,minus))}
***********************************************
*Charge computation*
***********************************************
Echarge charge 0 value={SDT(I(Emem))}
***********************************************
* WINDOW FUNCTIONS
* FOR NONLINEAR DRIFT MODELING *
***********************************************
*window function, according to Joglekar
.func f(x,p)={1-(2*x-1)^(2*p)}
*proposed window function
;.func f(x,i,p)={1-(x-stp(-i))^(2*p)}
.ENDS memristor
.ends nor
.ends and2
.ends
Netlist for MTL cell in NOR logic
vddnvdd 0 1
vccnvcc 0 1
v1 in1 0 PULSE(0 1 5u 1n 1n 10u 20u)
v2 in2 0 PULSE(0 1 10u 1n 1n 20u 40u)
xr1 in1 nvo memristor
xr2 in2 nvo memristor
XOPAMP nvo out1 opamp
M1 nvdd out1 output nvdd PMOS L=0.24U W=1U
M2 output out1 0 0 NMOS L=0.24U W=.36U
.tran 80u
.MODEL NMOS NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3728287
+K1 = 0.4864243 K2 = -1.409657E-4 K3 = 1E-3
+K3B = 2.825499 W0 = 1E-7 NLX = 1.888392E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.4506053 DVT1 = 0.550849 DVT2 = -0.5
+U0 = 288.0462132 UA = -1.405775E-9 UB = 2.623003E-18
+UC = 3.629325E-11 VSAT = 1.338206E5 A0 = 1.7824214
+AGS = 0.3184507 B0 = -3.027093E-8 B1 = -1E-7
+KETA = -7.187156E-3 A1 = 0 A2 = 0.5020225
+RDSW = 200 PRWG = 0.3401424 PRWB = 0.0544682
+WR = 1 WINT = 0 LINT = 3.714594E-12
+XL = 0 XW = -4E-8 DWG = -1.815918E-8
+DWB = 1.091895E-9 VOFF = -0.0921074 NFACTOR = 1.5957345
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 5.73523E-3 ETAB = 1.682537E-4
+DSUB = 0.038118 PCLM = 1.7102415 PDIBLC1 = 0.9099192
+PDIBLC2 = 3.201179E-3 PDIBLCB = 0.0309473 DROUT = 1
+PSCBE1 = 7.911377E10 PSCBE2 = 5.009298E-10 PVAG = 9.207919E-3
+DELTA = 0.01 RSH = 4 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.12E-10 CGSO = 4.12E-10 CGBO = 7E-10
+CJ = 1.79611E-3 PB = 0.99 MJ = 0.4682401
+CJSW = 4.500633E-10 PBSW = 0.9370045 MJSW = 0.3038281
+CJSWG = 3.29E-10 PBSWG = 0.9370045 MJSWG = 0.3038281
+CF = 0 PVTH0 = -7.974754E-3 PRDSW = -10
+PK2 = 5.306978E-3 WKETA = 8.666091E-3 LKETA = -9.033715E-3 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.5414189
+K1 = 0.6333125 K2 = 1.11193E-3 K3 = 0.0949758
+K3B = 10.0438776 W0 = 1E-6 NLX = 3.540373E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.6693896 DVT1 = 0.735565 DVT2 = -0.2439268
+U0 = 100 UA = 9.248319E-10 UB = 1E-21
+UC = -1E-10 VSAT = 1.577465E5 A0 = 0.9984451
+AGS = 0.1179402 B0 = 1.80539E-7 B1 = 8.788144E-7
+KETA = 0.0116764 A1 = 0.0252278 A2 = 0.3
+RDSW = 1.09093E3 PRWG = 0.150348 PRWB = -0.1482303
+WR = 1 WINT = 0 LINT = 2.8873E-8
+XL = 0 XW = -4E-8 DWG = -3.637876E-8
+DWB = -7.44149E-10 VOFF = -0.1180736 NFACTOR = 1.0742561
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.9070262 ETAB = -0.1833152
+DSUB = 1.5 PCLM = 1.3317254 PDIBLC1 = 8.162344E-3
+PDIBLC2 = 5.999554E-7 PDIBLCB = -4.026019E-4 DROUT = 0.1118588
+PSCBE1 = 8E10 PSCBE2 = 2.513346E-6 PVAG = 5.04939E-3
+DELTA = 0.01 RSH = 3 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.52E-10 CGSO = 4.52E-10 CGBO = 7E-10
+CJ = 1.86424E-3 PB = 0.985552 MJ = 0.4701753
+CJSW = 3.840487E-10 PBSW = 0.8 MJSW = 0.3085832
+CJSWG = 2.5E-10 PBSWG = 0.8 MJSWG = 0.3085832
+CF = 0 PVTH0 = 4.281542E-3 PRDSW = -0.4907077
+PK2 = 2.539815E-3 WKETA = 0.0275407 LKETA = -7.009864E-3 )
.subcktopampnvo op1
****************reference voltage of opamp VOS**********************************************
VOS 1 0 DC 0.1
* Power Supplies
VDD 3 0 DC 1
VSS 4 0 DC -1
* Netlist for CMOS COMPARATOR in Pwell
M1 5 1 7 4 NMOS W=.24U L=.24U
M2 6 nvo 7 4 NMOS W=.24U L=.24U
M3 5 5 3 3 PMOS W=.31992U L=.24U
M4 6 5 3 3 PMOS W=.31992U L=.24U
M5 7 9 4 4 NMOS W=.24U L=.24U
M6 op1 6 3 3 PMOS W=2.55984U L=.24U
M7 op1 9 4 4 NMOS W=.96U L=.24U
M8 9 9 4 4 NMOS W=.96U L=.24U
* External Components
CL op1 0 .2pF
RB 9 0 175K
* SPICE Parameters
.ends
.SUBCKT memristor Plus Minus PARAMS:
+ Ron=10K Roff=100K Rinit=80K D=10N uv=10F p=1
***********************************************
* DIFFERENTIAL EQUATION MODELING *
***********************************************
Gx 0 x value={ I(Emem)*uv*Ron/D^2*f(V(x),p)}
Cx x 0 1 IC={(Roff-Rinit)/(Roff-Ron)}
Raux x 0 1T
* RESISTIVE PORT OF THE MEMRISTOR *
*******************************
Emem plus aux value={-I(Emem)*V(x)*(Roff-Ron)}
Roff aux minus {Roff}
***********************************************
*Flux computation*
***********************************************
Eflux flux 0 value={SDT(V(plus,minus))}
***********************************************
*Charge computation*
***********************************************
Echarge charge 0 value={SDT(I(Emem))}
***********************************************
* WINDOW FUNCTIONS
* FOR NONLINEAR DRIFT MODELING *
***********************************************
*window function, according to Joglekar
.func f(x,p)={1-(2*x-1)^(2*p)}
*proposed window function
;.func f(x,i,p)={1-(x-stp(-i))^(2*p)}
.ENDS memristor
Netlist for two input proposed cell using AND gate
vddnvdd 0 1
vccnvcc 0 1
v1 in1 0 1
v2 in2 0 1
xand2 op in1 in2 nvddnvcc and2
.op
.subckt and2 out in1 in2 nvddnvcc
x_or1 op1 in1 in1nvddnvcc or
x_or2 op2 in2 in2nvddnvcc or
x_or3 out op1 op2 nvddnvcc or
.subckt or out2 in1 in2 nvddnvcc
vrefnref 0 .1
xr1 in1 nvo memristor
xr2 in2 nvo memristor
*xronvo 0 memristor
XOPAMP nvo out1 opamp
M1 nvdd out1 out2 nvdd PMOS L=0.24U W=1U
M2 out2 out1 0 0 NMOS L=0.24U W=.36U
*M3 nvdd out2 out nvdd PMOS L=0.24U W=1U
*M4 out out2 0 0 NMOS L=0.24U W=.36U
.subcktopampnvo op1
VOS 1 0 DC 0.1
* Power Supplies
VDD 3 0 DC 1
VSS 4 0 DC -1
* Netlist for CMOS COMPARATOR in Pwell
M1 5 1 7 4 NMOS W=.24U L=.24U
M2 6 nvo 7 4 NMOS W=.24U L=.24U
M3 5 5 3 3 PMOS W=.31992U L=.24U
M4 6 5 3 3 PMOS W=.31992U L=.24U
M5 7 9 4 4 NMOS W=.24U L=.24U
M6 op1 6 3 3 PMOS W=2.55984U L=.24U
M7 op1 9 4 4 NMOS W=.96U L=.24U
M8 9 9 4 4 NMOS W=.96U L=.24U
* External Components
CL op1 0 .2pF
RB 9 0 175K
* SPICE Parameters
.ends
.MODEL NMOS NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3728287
+K1 = 0.4864243 K2 = -1.409657E-4 K3 = 1E-3
+K3B = 2.825499 W0 = 1E-7 NLX = 1.888392E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.4506053 DVT1 = 0.550849 DVT2 = -0.5
+U0 = 288.0462132 UA = -1.405775E-9 UB = 2.623003E-18
+UC = 3.629325E-11 VSAT = 1.338206E5 A0 = 1.7824214
+AGS = 0.3184507 B0 = -3.027093E-8 B1 = -1E-7
+KETA = -7.187156E-3 A1 = 0 A2 = 0.5020225
+RDSW = 200 PRWG = 0.3401424 PRWB = 0.0544682
+WR = 1 WINT = 0 LINT = 3.714594E-12
+XL = 0 XW = -4E-8 DWG = -1.815918E-8
+DWB = 1.091895E-9 VOFF = -0.0921074 NFACTOR = 1.5957345
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 5.73523E-3 ETAB = 1.682537E-4
+DSUB = 0.038118 PCLM = 1.7102415 PDIBLC1 = 0.9099192
+PDIBLC2 = 3.201179E-3 PDIBLCB = 0.0309473 DROUT = 1
+PSCBE1 = 7.911377E10 PSCBE2 = 5.009298E-10 PVAG = 9.207919E-3
+DELTA = 0.01 RSH = 4 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.12E-10 CGSO = 4.12E-10 CGBO = 7E-10
+CJ = 1.79611E-3 PB = 0.99 MJ = 0.4682401
+CJSW = 4.500633E-10 PBSW = 0.9370045 MJSW = 0.3038281
+CJSWG = 3.29E-10 PBSWG = 0.9370045 MJSWG = 0.3038281
+CF = 0 PVTH0 = -7.974754E-3 PRDSW = -10
+PK2 = 5.306978E-3 WKETA = 8.666091E-3 LKETA = -9.033715E-3 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.5414189
+K1 = 0.6333125 K2 = 1.11193E-3 K3 = 0.0949758
+K3B = 10.0438776 W0 = 1E-6 NLX = 3.540373E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.6693896 DVT1 = 0.735565 DVT2 = -0.2439268
+U0 = 100 UA = 9.248319E-10 UB = 1E-21
+UC = -1E-10 VSAT = 1.577465E5 A0 = 0.9984451
+AGS = 0.1179402 B0 = 1.80539E-7 B1 = 8.788144E-7
+KETA = 0.0116764 A1 = 0.0252278 A2 = 0.3
+RDSW = 1.09093E3 PRWG = 0.150348 PRWB = -0.1482303
+WR = 1 WINT = 0 LINT = 2.8873E-8
+XL = 0 XW = -4E-8 DWG = -3.637876E-8
+DWB = -7.44149E-10 VOFF = -0.1180736 NFACTOR = 1.0742561
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.9070262 ETAB = -0.1833152
+DSUB = 1.5 PCLM = 1.3317254 PDIBLC1 = 8.162344E-3
+PDIBLC2 = 5.999554E-7 PDIBLCB = -4.026019E-4 DROUT = 0.1118588
+PSCBE1 = 8E10 PSCBE2 = 2.513346E-6 PVAG = 5.04939E-3
+DELTA = 0.01 RSH = 3 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.52E-10 CGSO = 4.52E-10 CGBO = 7E-10
+CJ = 1.86424E-3 PB = 0.985552 MJ = 0.4701753
+CJSW = 3.840487E-10 PBSW = 0.8 MJSW = 0.3085832
+CJSWG = 2.5E-10 PBSWG = 0.8 MJSWG = 0.3085832
+CF = 0 PVTH0 = 4.281542E-3 PRDSW = -0.4907077
+PK2 = 2.539815E-3 WKETA = 0.0275407 LKETA = -7.009864E-3 )
.SUBCKT memristor Plus Minus PARAMS:
+ Ron=10K Roff=100K Rinit=80K D=10N uv=10F p=1
***********************************************
* DIFFERENTIAL EQUATION MODELING *
***********************************************
Gx 0 x value={ I(Emem)*uv*Ron/D^2*f(V(x),p)}
Cx x 0 1 IC={(Roff-Rinit)/(Roff-Ron)}
Raux x 0 1T
* RESISTIVE PORT OF THE MEMRISTOR *
*******************************
Emem plus aux value={-I(Emem)*V(x)*(Roff-Ron)}
Roff aux minus {Roff}
***********************************************
*Flux computation*
***********************************************
Eflux flux 0 value={SDT(V(plus,minus))}
***********************************************
*Charge computation*
***********************************************
Echarge charge 0 value={SDT(I(Emem))}
***********************************************
* WINDOW FUNCTIONS
* FOR NONLINEAR DRIFT MODELING *
***********************************************
*window function, according to Joglekar
.func f(x,p)={1-(2*x-1)^(2*p)}
*proposed window function
;.func f(x,i,p)={1-(x-stp(-i))^(2*p)}
.ENDS memristor
.ENDS
.ends and2
Netlist for two input proposed cell using XOR gate
* biasing the op amp
* two voltage sources are declared vdd and vcc . the negative terminals are grounded (hence the value 0v). The positive node is named nvdd and nvcc respectively and a voltage
*of 1V each is assigned.
vddnvdd 0 1
vccnvcc 0 1
* declaring two voltage sources V1 and v2 . v1’s negative node is grounded and positive node is named in1 and the voltage across it is 1v.
*v2’s negative node is grounded and positive node is named in2 and the voltage across it is 0v. V1 and V2 are used for inputing the voltage values to xor gate.
v1 in1 0 PULSE(0 1 5u 1n 1n 10u 20u)
v2 in2 0 PULSE(0 1 10u 1n 1n 20u 40u)
* coniguring the xor for simulation X_xor means the name of the circuit and the xor at the end of the command means that that we are invoking a circuit defined as xor. xor has got 1 output pin which is named as op, two input pins connected to
* the nodes in1 and in2. their power oinsvdd and vcc connected to nvdd and nvcc .
x_xor op in1 in2 nvddnvccxor
* op is the command for simulation
.tran 80u
* Describing xor gate using nor gates
* as mentioned earlier X_or1, x_or2 ets are labels. They are invoking a circuit defined by nor2 (which is actually a 2 bit nor gate (defined later))
.subcktxor out in1 in2 nvddnvcc
x_or1 op1 in1 in1nvddnvcc nor2
x_or2 op2 in2 in2nvddnvcc nor2
x_or3 op3 in1 in2 nvddnvcc nor2
x_or4 op4 op1 op2 nvddnvcc nor2
x_or5 out op3 op4 nvddnvcc nor2
.subckt nor2 out2 in1 in2 nvddnvcc
*vrefnref 0 .1
xr1 in1 nvo memristor
xr2 in2 nvo memristor
*xronvo 0 memristor
XOPAMP nvo out1 opamp
M1 nvdd out1 out2 nvdd PMOS L=0.24U W=1U
M2 out2 out1 0 0 NMOS L=0.24U W=.36U
*M3 nvdd out2 out nvdd PMOS L=0.24U W=1U
*M4 out out2 0 0 NMOS L=0.24U W=.36U
* basic op amp using 8 transistrs.
.subcktopampnvo op1
VOS 1 0 DC 0.1
* Power Supplies
VDD 3 0 DC 1
VSS 4 0 DC -1
* Netlist for CMOS COMPARATOR in Pwell
M1 5 1 7 4 NMOS W=.24U L=.24U
M2 6 nvo 7 4 NMOS W=.24U L=.24U
M3 5 5 3 3 PMOS W=.31992U L=.24U
M4 6 5 3 3 PMOS W=.31992U L=.24U
M5 7 9 4 4 NMOS W=.24U L=.24U
M6 op1 6 3 3 PMOS W=2.55984U L=.24U
M7 op1 9 4 4 NMOS W=.96U L=.24U
M8 9 9 4 4 NMOS W=.96U L=.24U
* External Components
CL op1 0 .2pF
RB 9 0 175K
* SPICE Parameters
.ends
* device model obtained from mosis website – nmos and pmos
.MODEL NMOS NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3728287
+K1 = 0.4864243 K2 = -1.409657E-4 K3 = 1E-3
+K3B = 2.825499 W0 = 1E-7 NLX = 1.888392E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.4506053 DVT1 = 0.550849 DVT2 = -0.5
+U0 = 288.0462132 UA = -1.405775E-9 UB = 2.623003E-18
+UC = 3.629325E-11 VSAT = 1.338206E5 A0 = 1.7824214
+AGS = 0.3184507 B0 = -3.027093E-8 B1 = -1E-7
+KETA = -7.187156E-3 A1 = 0 A2 = 0.5020225
+RDSW = 200 PRWG = 0.3401424 PRWB = 0.0544682
+WR = 1 WINT = 0 LINT = 3.714594E-12
+XL = 0 XW = -4E-8 DWG = -1.815918E-8
+DWB = 1.091895E-9 VOFF = -0.0921074 NFACTOR = 1.5957345
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 5.73523E-3 ETAB = 1.682537E-4
+DSUB = 0.038118 PCLM = 1.7102415 PDIBLC1 = 0.9099192
+PDIBLC2 = 3.201179E-3 PDIBLCB = 0.0309473 DROUT = 1
+PSCBE1 = 7.911377E10 PSCBE2 = 5.009298E-10 PVAG = 9.207919E-3
+DELTA = 0.01 RSH = 4 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.12E-10 CGSO = 4.12E-10 CGBO = 7E-10
+CJ = 1.79611E-3 PB = 0.99 MJ = 0.4682401
+CJSW = 4.500633E-10 PBSW = 0.9370045 MJSW = 0.3038281
+CJSWG = 3.29E-10 PBSWG = 0.9370045 MJSWG = 0.3038281
+CF = 0 PVTH0 = -7.974754E-3 PRDSW = -10
+PK2 = 5.306978E-3 WKETA = 8.666091E-3 LKETA = -9.033715E-3 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.5414189
+K1 = 0.6333125 K2 = 1.11193E-3 K3 = 0.0949758
+K3B = 10.0438776 W0 = 1E-6 NLX = 3.540373E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.6693896 DVT1 = 0.735565 DVT2 = -0.2439268
+U0 = 100 UA = 9.248319E-10 UB = 1E-21
+UC = -1E-10 VSAT = 1.577465E5 A0 = 0.9984451
+AGS = 0.1179402 B0 = 1.80539E-7 B1 = 8.788144E-7
+KETA = 0.0116764 A1 = 0.0252278 A2 = 0.3
+RDSW = 1.09093E3 PRWG = 0.150348 PRWB = -0.1482303
+WR = 1 WINT = 0 LINT = 2.8873E-8
+XL = 0 XW = -4E-8 DWG = -3.637876E-8
+DWB = -7.44149E-10 VOFF = -0.1180736 NFACTOR = 1.0742561
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.9070262 ETAB = -0.1833152
+DSUB = 1.5 PCLM = 1.3317254 PDIBLC1 = 8.162344E-3
+PDIBLC2 = 5.999554E-7 PDIBLCB = -4.026019E-4 DROUT = 0.1118588
+PSCBE1 = 8E10 PSCBE2 = 2.513346E-6 PVAG = 5.04939E-3
+DELTA = 0.01 RSH = 3 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 4.52E-10 CGSO = 4.52E-10 CGBO = 7E-10
+CJ = 1.86424E-3 PB = 0.985552 MJ = 0.4701753
+CJSW = 3.840487E-10 PBSW = 0.8 MJSW = 0.3085832
+CJSWG = 2.5E-10 PBSWG = 0.8 MJSWG = 0.3085832
+CF = 0 PVTH0 = 4.281542E-3 PRDSW = -0.4907077
+PK2 = 2.539815E-3 WKETA = 0.0275407 LKETA = -7.009864E-3 )
* declaring a memristor . Implementing the state equations directly .
.SUBCKT memristor Plus Minus PARAMS:
+ Ron=10K Roff=100K Rinit=80K D=10N uv=10F p=1
***********************************************
* DIFFERENTIAL EQUATION MODELING *
***********************************************
Gx 0 x value={ I(Emem)*uv*Ron/D^2*f(V(x),p)}
Cx x 0 1 IC={(Roff-Rinit)/(Roff-Ron)}
Raux x 0 1T
* RESISTIVE PORT OF THE MEMRISTOR *
*******************************
Emem plus aux value={-I(Emem)*V(x)*(Roff-Ron)}
Roff aux minus {Roff}
***********************************************
*Flux computation*
***********************************************
Eflux flux 0 value={SDT(V(plus,minus))}
***********************************************
*Charge computation*
***********************************************
Echarge charge 0 value={SDT(I(Emem))}
***********************************************
* WINDOW FUNCTIONS
* FOR NONLINEAR DRIFT MODELING *
***********************************************
*window function, according to Joglekar
.func f(x,p)={1-(2*x-1)^(2*p)}
*proposed window function
;.func f(x,i,p)={1-(x-stp(-i))^(2*p)}
.ENDS memristor
.ENDS
.ends xor