Essay: Evolution of SONOS

The possibility of non-volatile MOS memory device was recognized. The memory transistor proposed by them was similar to MOS structure, except the gate structure was replaced by a layered structure of a thin oxide I1, a floating gate but conducting metal layer M1, a thick oxide I2, and an external metal gate M2 as shown in Figure 3.1. This device was referred to as MIMIS (metal-insulator-metal-insulator-semiconductor) cell.
Figure 3.1: Introduction to floating gate principle: the MIMIS structure[11].
The first dielectric I1 has to be sufficiently thin in order to obtain a high electric field to allow tunnelling of electrons toward the floating gate. These electrons are then captured to the conduction band of the floating gate M1, if the dielectric I2 is thick enough to prevent discharging. When the gate voltage is removed, the field in I1 is too small to allow back tunnelling. The injection mechanism to bring electrons to the floating gate is direct tunneling. To discharge the floating gate, a negative voltage pulse is applied at M2, removing the electrons from the floating gate by same direct tunneling mechanism. Direct tunneling programming mechanism imposes the use of very thin oxide layers (<5nm), which was difficult to achieve because any pinhole in I1 will cause all the charge stored on M1 to leak off. To overcome these technological constraints of MIMIS cell, the first solution was introduction of MNOS. In MNOS cell, the M1and I2 was replaced by a nitride layer, which contains high density of trapping centres to capture holes and electrons. These traps fulfil the storage function of M1 with the important difference that any pinhole in thin oxide layer (I1) will not result in complete discharge of the cell since individual traps is isolated from each other by the nitride. The MNOS device has the intrinsic advantage that both programming and erasing operations can be performed electrically. In the late 80's and early 90's, both n and p-channel SONOS device emerged with write/erase voltage of 5-12V. MNOS employed a 1 transistor per bit configuration based on the tri-gate transistor cell concept [15]. In this transistor only the centre part of the cell channel contained the programmable UTO-nitride sandwich structure. At both drain and source, a thicker oxide-nitride sandwich was used, which induced a fixed threshold voltage in the erased state and prevented the device from going into the depletion mode. These memory devices suffered from low-speed, limited-density, inherent read disturbance and the need for 2 to 3 voltage supplied to operate the memory. Erasure in MNOS is obtained by tunnelling of holes from the semiconductor to the nitride traps when VG is negative and sufficiently high. It is necessary to find a polysilicon gate technology. Replacing aluminium by polysilicon seems a simple approach but it is an unpractical one because, silicon/silicon nitride interface is unstable. This instability, observed in a SNOS [9] (poly Silicon-Nitride-Oxide-Silicon) memory capacitor has been remedied by employing a SONOS (poly Silicon-Oxide-Nitride-Oxide-Silicon) structure. It is a two transistor per bit configuration in which MOS acts as a select device whose implementation completely eliminated the problem of read disturbance [17]. The SNOS consists of a silicon nitride layer (20-40 nm) on top of the UTO on silicon. The programming of the cell is as follows: during the write operation, a high (positive voltage is applied to the gate with the well grounded. Electrons tunnel from the silicon conduction band into the nitride conduction band through Modified Fowler-Nordheim tunneling process and are trapped in the nitride traps, resulting in a positive threshold voltage shift. Erasing is achieved by grounding the gate and applying a high (positive) voltage to the well. This induces direct tunneling of holes from the silicon valence band into the nitride valence band, or the nitride traps [18, 19], resulting in a negative threshold voltage. During the off-state, the gate is grounded and the select transistor is required for proper operation within the array. By addressing the cell through the select transistor reading of the cell is done and by sensing the state of the SNOS transistor. The charge content within the nitride will be modified in time due to back tunnelling of charges through the UTO. Hole injection from the gate limit the memory window, a problem that becomes more severe for thinner nitride layers as charge stored in it is widely distributed. In the SONOS structure, the charge centroid is closer to the silicon surface. The presence of a SiO2 layer modifies the conditions which limit the amount of charge which can be stored in the nitride during writing or erasing. It also modifies the decay of the stored charge during retention. 3.2. Advantages of SONOS Over General Flash Memory 1. SONOS, charges are stored in the nitride layer in terms of structure. 2. SONOS offers radiation hardness [21] improvements over floating gate EEPROM technology. 3. Scaling of floating gate is limited in the lateral (gate-to-gate) direction also. Electrons which stores upon polysilicon gate exert an electric field on adjacent gates. In SONOS, the charges are electrically trapped in the nitride layer. So they do not interfere. 3.3. Structure and Theory of SONOS non-volatile memory device 3.3.1. Structure of SONOS device 1. SONOS, charges are stored in the nitride layer in terms of structure. 2. SONOS offers radiation hardness [21] improvements over floating gate EEPROM technology. 3. Scaling of floating gate is limited in the lateral (gate-to-gate) direction also. Electrons which stores upon polysilicon gate exert an electric field on adjacent gates. As the geometry scale down, this electric field becomes so strong that it unintentionally programs. 3.3. Structure and Theory of SONOS non-volatile memory device 3.3.1. Structure of SONOS device The device is similar to SNOS transistor but for an oxide layer between Silicon Nitride and polysilicon gate electrode. 3.3.2. Theory of SONOS structure Consider an MNOS structure under bias [22]. Voltage VG is applied to the gate electrode, Generally a volume distribution ?? of charges exits within each insulator and a surface density Q of charge exists at each interface as shown in Figure 3.2. The Poisson's equation given as: ??V +??/?? = 0 (3.1) 1. Use of an aluminium gate in an MNOS does not allow the manufacture of dense and high speed circuits because Al deposition is not a self-aligned process. The integration of